1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of outputting data signals from the semiconductor memory device.
2. Description of the Related Art
In recent years, a high-speed operation has been required in a semiconductor memory device. As a method of speeding up the operations of the semiconductor memory device such as a read operation and a write operation, it could be considered to control a data bus. In a period of an output operation, a signal level of a power supply voltage VCC or a ground voltage GND is conventionally applied to the data bus. However, this method is insufficient. However, the operation speed tends to delay due to a large parasitic capacitance of the data bus. For this reason, the voltage of (½)VCC is applied to the data bus in an equalizing period. Thus, the data bus is pre-charged and the output operation is sped-up after the equalizing period.
FIG. 1 is a block diagram showing a configuration of a conventional flash memory as a semiconductor memory device. The flash memory 100 is provided on a semiconductor chip. The flash memory 100 includes an address buffer section 2, a plurality of plates 3-1 to 3-6, an output bus section 116, and an input/output buffer section 6, a control circuit 104, and a boosting circuit 5. Terminals 1-1 to 1-n (n is an integer of one or more) are connected with the address buffer section 2. Terminals 7-1 to 7-n are connected with the input/output buffer section 6. The terminals 7-1 to 7-n are provided for the terminals 1-1 to 1-n, respectively. The output bus section 116 includes output bus units 116-1 to 116-n. The output bus units 116-1 to 116-n are allocated to the terminal 7-1 to 7-n, respectively. The output bus units 116-1 to 116-n are connected with the respective plates 3-1 to 3-6 and the input/output buffer section 6.
An address is supplied from the external of the flash memory 100 to the address buffer section 2 through the terminals 1-j (j=1, 2, . . . , n). The address buffer section 2 outputs an address signal to each of the plates 3-1 to 3-6 in accordance with a signal level of an internal circuit. The plate 3-k (k=1 to 6) outputs data as a data output signal based on the address signal. The data output signals output from the plates 3-k are gathered to the output bus units 116-j and are supplied to the input/output buffer section 6. The input/output buffer section 6 generates output data after adjusting the signal levels of the output data signals in accordance with an external signal level, and outputs the output data outside the flash memory 100 through the terminals 7-j. The control circuit 104 receives control data from the input/output buffer section 6. The control circuit 104 determines an operation of the flash memory 100 based on the control data to generate control signals. The control circuit 104 distributes the control signals to the boosting circuit 5, the plates 3-j, and the output buses 116-j, to control the flash memory 100. The boosting circuit 5 distributes the boosted power supply voltage to the plates 3-j.
The plate 3-k (k=1, 2, . . . 6) is a unit of functional blocks of the flash memory 100, and includes sectors 13-1 to 13-n, a global row decoder 11-k, local row decoders 12-k, a column decoder 9-k, a sense amplifier circuit 15-k, a reference cell section 14-k, and a power supply switching section 8-k. The sense amplifier circuit 15-k includes sense amplifiers 15-k-j (15-k-1 to 15-k-n). The sectors 13-j (j=1 to n) are provided for the sense amplifiers 15-k-j, respectively. The sense amplifiers 15-k-j are provided for the output bus units 116-j, respectively. Each of the sectors 13-j is a minimum unit upon erasing its stored data, and includes a plurality of the memory cells. The power supply switching section 8-k switches the power supply voltage from the boosting circuit 5 in response to the control signal from the control circuit 104, and supplies to the global row decoder 11-k and the column decoder 9-k.
The address signal is distributed to the global row decoder 11-k, the local row decoders 12-k, and the column decoder 9-k in the plate 3-k. A row address of the address signal is decoded by the global row decoder 11-k and the local row decoder 12-k to select one of word lines. A column address of the address signal is decoded by the column decoder 9-k to select one of bit lines. The selected word line and selected bit line specify one of the memory cells, from which data is read out, and into which the data is written. The data read out from the selected memory cell is compared with data read out from the reference cell section 14 by the sense amplifier circuit 15-k. The sense amplifier circuit 15-k outputs the comparison result to the output bus section 116-j as the above-mentioned data output signal.
FIG. 2 shows the control circuit 104 and the output bus unit 116-j of the output bus section 116. As shown in FIG. 2, the control circuit 104 outputs a first selection signal A or a second selection signal B, and a reset signal C alternately to the output bus unit 116-j as the above-mentioned control signals. For instance, the first selection signal A indicates an active state when the signal level is low, and an inactive state when the signal level is high. The second selection signal B indicates an active state when the signal level is low, and an inactive state when the signal level is high. The reset signal C indicates an active state when the signal level is low, and an inactive state when the signal level is high.
The output bus section 116-j includes a data bus 120, a first output section 121 a second output section 122, and a P-channel transistor 123. The input/output buffer section 6 is connected with the data bus 120.
The first output section 121 has inverters 121-1 to 121-3. the input of the inverter 121-1 is connected with the output of the sense amplifier 15-1-j in the plates 3-1, and the input of the inverter 121-2 is connected with the output of the sense amplifier 15-2-j in the plates 3-2. The outputs of the inverters 121-1 to 121-3 are connected with the data bus 120. The inverters 121-1 to 121-3 are connected with and controlled by the control circuit 104. Each of the inverters 121-1 to 121-3 inverts the signal output from the corresponding sense amplifier in response to the first selection signal A of the low level from the control circuit 104, and outputs the inverted signal. The second output section 122 has inverters 122-1 to 122-3. The input of the inverter 122-1 is connected with the output of the sense amplifier circuit 15-4-j in the plate 3-4, and the input of the inverters 122-2 is connected with the output of the sense amplifier circuit 15-5-j in the plate 3-5. The outputs of the inverters 122-1 to 122-3 are connected with the data bus 120. The inverters 122-1 to 122-3 are connected with and controlled by the control circuit 104. Each of the inverters 122-1 to 122-3 inverts a signal output from the corresponding sense amplifier in response to the second selection signal B of the low level from the control circuit 104, and outputs the inverted signal.
The voltage of (½)VCC that is a half of the power supply voltage VCC is supplied to the source of the P-channel transistor 123. The drain of the P-channel transistor 123 is connected with the data bus 120. The gate of the P-channel transistor 123 is connected with the control circuit 104. The reset signal C of the low level from the control circuit 104 is supplied to the gate of the P-channel transistor 123.
FIGS. 3A to 3D are timing charts showing an operation of the output bus section 116-j in the flash memory 100. The control unit 104 controls the P-channel transistor 123 so that an action period ACT and an equalizing period EQC are repeated alternately. The control unit 104 outputs the first selection signal A of the low level or the second selection signal B of the low level to specify the action period ACT. Also, the control unit 104 outputs the reset signal C of the low level to specify the equalizing period EQC.
First, the control circuit 104 determines the operation to be carried out by the flash memory 100 based on the control data from the address buffer section 2. As a result, for instance, it is supposed that the control circuit 104 determines that the sense amplifier circuit 15-1-1 in the plate 3-1 should output the data output signal to the output bus unit 116-1. In this case, the control unit 104 outputs the first selection signal A of the low level to specify the action period ACT.
In the action period ACT, it is supposed that the signal level of the data output signal to be output from the sense amplifier circuit 15-1-1 onto the output bus unit 116-1 indicates a ground voltage GND. The inverter 121-1 of the first output circuit 121 in the output bus unit 116-1 inverts the data output signal from the sense amplifier circuit 15-1-1 in response to the first selection signal A of low level and outputs the inverted signal to the data bus 120. At this time, the inverter 121-1 outputs the data output signal of a power supply voltage VCC. A signal level O applied to the data bus 120 indicates the power supply voltage VCC. In the action period ACT, the input/output buffer section 6 inverts the signal output onto the data bus 120. The input/output buffer section 6 generates output data adjusted to an external signal level based on the ground voltage GND, and then outputs the output data to the external of the flash memory 100 through the terminal 7-1.
Next, the control circuit 104 outputs the reset signal C of the low level to specify the equalizing period EQC. In the equalizing period EQC, the P-channel transistor 123 of the output bus unit 116-1 is turned on in response to the reset signal C of the low level, and applies the Voltage (½)VCC to the data bus 120 compulsorily. In this way, in the equalizing period EQC in the flash memory 100, the Voltage of (½)VCC is applied to the data bus 120. That is, the data bus 120 is pre-charged to the Voltage (½)VCC. Thus, the operation such as a read operation is speeded up in the action period ACT following to the equalizing period EQC. However, the data bus 120 is compulsorily pre-charged to the voltage of (½)VCC in the equalizing period EQC without no relation to the voltage applied to the data bus 120 in the action period ACT. Therefore, the power supply voltage VCC drops possibly. In this case, the flash memory 100 cannot carry out the operation at high speed.
Also, in the flash memory 100, the data bus 120 is compulsorily pre-charged to the voltage of (½)VCC in the equalizing period EQC without any relation to the voltage applied to the data bus 120 in the action period ACT. Therefore, power consumption of the flash memory 100 increases.
In conjunction with the above description, another conventional semiconductor memory device is disclosed in Japanese Laid Open Patent Application (JP-P2000-149565A). the semiconductor memory device in this conventional example includes a data bus driver, an I/O line, and a data bus. The output of a sense amplifier and the output of the data bus driver are connected with the I/O line. The output of the data bus driver is connected with the data bus. An equalizing circuit is connected to the I/O line and the data bus. The signal from the sense amplifier is applied to the I/O line. The data bus driver inverts the signal applied to the I/O line to output the inverted signal to the data bus. The equalizing circuit stores the signal applied to the I/O line in a capacitor. The equalizing circuit generates a signal with a signal level between the voltage level of the capacitor and the voltage level of the data bus in response to an equalized signal. Thus, the equalizing circuit outputs the generated signal to the data bus.